this post was submitted on 25 Oct 2025
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Two V-Cache CCDs just don't make sense for consumer use-cases is the point here.
Because of the latency topology you'd only see a benefit if both CCDs were running independent programs that are more strictly sensitive to latency than compute throughput. That's a very niche subset of uses, and like I said, ideal for a GSP deployment. This should be a product, but in the EPYC 4005 family.
Otherwise, you're better off with some sort of heterogeneous topology, one can imagine an 8 core V-Cache CCD paired with a 16 c-core CCD design (this is very roughly what Intel is pursuing with upcoming products) which offers compelling utility even in the consumer space.
That or you run properly designed software. Pinning threads to CPUs and separating data isn't magic. Claiming "this is useless for [extremely broad group of people]" is just a weird and ignorant statement. There are literally people running servers at home.
Which is why I've said three times now it should be an EPYC 4005 product.