RISC-V

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RISC-V (pronounced “risk-five”) is a license-free, modular, extensible instruction set architecture (ISA).

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RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint (www.tomshardware.com)

submitted 1 month ago by cm0002@lemmy.zip to c/riscv@programming.dev

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[–] stormeuh@lemmy.world 1 points 1 month ago (1 children)

Eating the market from the bottom up is also the strategy ARM used to get this successful. But then again, x86 stagnating (or nearing EOL, but I won't make predictions about that) will also have contributed significantly to their success in the high-end market.

[–] LeFantome@programming.dev 2 points 1 month ago

Agreed. They are following the ARM playbook but faster. The success of ARM has made it easier. ARM is just starting to take on the server side and RISC-V is about to enter that space with Tenstorrent, Alibaba, Ventana, and others. Alibaba has a talk on the C930 at the RISC-V summit later this month. Tenstorrent has a talk on Ascalon with “now available” in the title. Akeana has a few talks bragging about performance. There is a suspiciously high number of Qualcomm appearances as well.

Intel could really get squeezed on the server. They have to compete not just with AMD but with both ARM and RISC-V. If you are building out cloud infrastructure that is going to be running end-user Python scripts that wire together AWS web services, who cares what the ISA is?

I think ARM made a big mistake suing Qualcomm over X Elite. If I was a chip maker, I would use RISC-V simply to avoid the risk of ARM trying to block or dictate my business model.

And if you are doing AI at the edge, the regular CPU hardly matters. What advantages do ARM and x86 offer over RISC-V there? If none, an open ISA makes sense. Again, just for the control and lack of legal risk if nothing else.