Steam Hardware

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A place to discuss and support all Steam Hardware, including Steam Deck, Steam Machine, Steam Frame, and SteamOS in general.

As Lemmy doesn't have flairs yet, you can use these prefixes to indicate what type of post you have made, eg:
[Flair] My post title

The following is a list of suggested flairs:
[Deck] - Steam Deck related.
[Machine] - Steam Machine related.
[Frame] - Steam Frame related.
[Discussion] - General discussion.
[Help] - A request for help or support.
[News] - News about the deck.
[PSA] - Sharing important information.
[Game] - News / info about a game on the deck.
[Update] - An update to a previous post.
[Meta] - Discussion about this community.

If your post is only relevant to one hardware device (Deck/Machine/Frame/etc) please specify which one as part of the title or by using a device flair.

These are not enforced, but they are encouraged.

Rules:

Follow the rules of Sopuli
Posts must be related to Steam Hardware or Steam OS in an obvious way.
No piracy, there are other communities for that.
Discussion of emulators are allowed, but no discussion on how to illegally acquire ROMs.
This is a place of civil discussion, no trolling.
Have fun.

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founded 4 years ago

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Fubarberry@sopuli.xyz

Moxvallix@sopuli.xyz

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Valve 'Fremont' APU breaks cover on Geekbench, most likely for a future console (www.club386.com)

submitted 3 months ago by Fubarberry@sopuli.xyz to c/steamdeck@sopuli.xyz

35 comments fedilink hide all child comments

New steam controller expected to release alongside it. This also should push back estimates of when to expect a Steam Deck 2, since valve is probably putting most of their hardware efforts towards this instead.

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[–] The_Decryptor@aussie.zone 7 points 3 months ago* (last edited 3 months ago) (1 children)

1 of the main things i think is how memory is laid out is different somehow? so every memory access needs extra clock cycles to accomplish in standard arm64

It's down to "memory ordering", as different cores interact with RAM there's rules that govern how those cores see changes made by other cores. ARM systems are "weak", so rely on developers to be explicit about the sharing, while x86's "Total Store Order" is considered "strong" and relies on the hardware to disentangle it all so software can make assumptions and play fast and loose.

You can do software emulation of strong memory ordering on a weak system, but it's slow. What Apple did was provide a hardware implementation of strong ordering in their ARM chips, and Rosetta enables that when running x86 code, so users don't encounter that slowdown.

[–] pupbiru@aussie.zone 3 points 3 months ago

amazing! thanks for the clarification